1. Field of the Invention
The present invention relates to a semiconductor chip package and a method for fabricating the same, and more particularly to an FBGA (fine pitch ball grid array) type semiconductor chip package and a method for fabricating the same.
2. Description of the Prior Art
Recently, as information media, such as computers have been widely used, the semiconductor industry makes great strides. In a functional aspect, a semiconductor device must be operated at a high speed with a large storage capacity. To this end, the semiconductor technology has been developed to improve the integration degree, reliability and response speed of the semiconductor device.
Particularly, the semiconductor chip package has been developed from a pin-insertion type semiconductor chip package to a surface-mounting type semiconductor chip package in order to increase packaging density. Currently, an FBGA (fine pitch ball grid array) type semiconductor chip package has been developed in order to increase packaging density. Such an FBGA type semiconductor chip package has a stacked structure so that the packaging density thereof will be further increased.
One example of such FBGA type semiconductor chip packages is disclosed in U.S. Pat. No. 6,127,194, issued to Mahanpour, et al.
Referring to FIG. 1, an FBGA type semiconductor chip package includes a circuit board 10 and a semiconductor chip 12. The circuit board 10 is formed with a core 110, a copper trace 112, and a solder mask 114. In addition, the semiconductor chip 12 has protective layers 120a and 120b, which are sequentially aligned at an uppermost part of the semiconductor chip 12, and a fuse 122, which is formed by exposing metal. In addition, a solder ball 16 is formed on the circuit board 10 such that the circuit board 10 is connected to external devices. Herein, the circuit board 10 is bonded to the semiconductor chip 12 by means of adhesive 14, such as a tape.
In addition, after bonding the circuit board 10 to the semiconductor chip 12, an HAST (highly accelerated stress test) is carried out for testing reliability of the semiconductor device. One example of the HAST is disclosed in U.S. Pat. No. 6,265,550, issued to Herr, et al.
However, when the HAST has been finished, it is frequently found that protective layers 120a and 120b of the semiconductor chip 12 are delaminated. Such a delamination phenomenon may be generated because material the copper trace 112 formed on the circuit board 10 migrates to a predetermined portion of the semiconductor chip 12 in which the fuse 122 is formed.
Therefore, as mentioned above, when the HAST is carried out for the conventional semiconductor chip package, a delamination phenomenon may frequently occur between the circuit board and the semiconductor chip. Thus, the conventional semiconductor chip package represents inferior reliability.